1. Field of the Invention
The present invention relates to a multi-level integrated circuit wiring structure formed from a single metal deposit.
2. Background Art
Once a semiconductor substrate has been processed to form the desired circuits, the device must then be provided with a wiring structure. A term which is synonymous with "wiring structure" is that of "metallization structure". A first prior art method which utilizes a layer-by-layer construction approach to provide a wiring structure is shown in FIG. 1.
In detailing the first steps in this approach, a semiconductor substrate 100 is processed to provide semiconductor circuits 102 and 104 and then an insulating layer 106 is formed on top of the semiconductor substrate 100. Next, the insulating layer 106 is masked and etched to provide wiring trenches 107 and 111. These wiring trenches 107 and 111 are etched completely through the insulating layer 106 at locations which correspond to the locations of the semiconductor circuits 102 and 104, respectively. The wiring trenches 107 and 111 are then filled with a conductive material 110 and 114.
Once the wiring trenches 107 and 111 have been filled with the conductive material, the surface of the insulating layer 106 is planarized. The remaining construction of the desired wiring structure proceeds with the formation of successive insulating layers 118, 124, 130 and 136, each of which is masked and etched to form wiring trenches which are then filled with a conductive material.
In the example illustrated in FIG. 1, two resulting wiring structures are shown. The first, consisting of the conductive material deposits 110, 120, 126, 132 and 138, provides connection to the semiconductor circuit 102, and the second, consisting of the conductive material deposits 114, 122, 128 and 134, provides connection to the semiconductor circuit 104.
The above approach to constructing a multi-level wiring structure is well known in the art, for example, U.S. Pat. No. 3,838,442 - Humphreys (assigned to the assignee of this application), the teaching of which is incorporated herein by reference.
The multiple layer approach shown in the example of FIG. 1 is disadvantageous in several respects. First, an excessive number of masking and deposition steps are required at the end-of-the-line processing stage, whereby manufacturing yield may be lowered. Next, and more importantly, the resulting wiring structure of FIG. 1 a number of metallic interfaces, are formed within the wiring structure. These interfaces add to the overall wiring structure resistance. Furthermore, these localized high resistance areas are prone to overheating and thermal failure.
As a result of the trend of the semiconductor industry toward extremely dense semiconductor circuits, the contact resistance of wiring structures has become a large concern. In this regard, the excessive contact resistances encountered in the prior art approach of FIG. 1 have been found intolerable.
A second prior art approach, which reduces wiring structure metallic interfaces and the number of processing steps, is that of the stud-down approach shown in FIG. 2. In FIG. 2, features which are the same as those in FIG. 1 have been designated by the same reference numerals.
In FIG. 2, the semiconductor substrate 100 has been processed to form the semiconductor circuits 102 and 104. In detailing the processing steps to form the wiring structure, an insulating layer 200 is formed on top of the semiconductor substrate 100. The insulating layer 200 is masked with a first mask, and then partially etched to form wiring troughs 202 and 204. A second mask is then applied, and the insulating layer 200 is further etched to form stud-down vias 206 and 208 which extend down from the bottom portion of the wiring troughs 202 and 204, respectively.
Methods of forming stud-down via wiring structures are well known in the art. As an example, U S. Pat. No. 3,904.454 issued to Magdo et al. and assigned to the assignee of this application, discloses a method of forming a stud-down via using a first mask to define a slot in a first direction, and then using a second mask to define and etch an intersecting slot in an intersecting direction. The stud-down via is formed at the intersection of the two etched slots. Another disclosure of the stud-down via approach is found in U.S. Pat. No. 4,541.893 issued to Knight.
Once formed, the wiring troughs 202 and 204 and the stud-down vias 206 and 208 are filled with a conductive material. The entire surface of the insulating layer 200 is then planarized.
To form the next portion of the desired wiring structure, the wiring troughs 216 and 218 and their corresponding stud-down vias 220 and 222 are etched in an insulating layer 214. Once etched, the wiring troughs 216 and 218 and the stud-down vias 220 and 222 are filled with conductive materials 224 and 226, respectively. The wiring structure is completed by forming trench 232 in an insulating layer 228 and filling the trench with a conductive material 230.
In comparing the wiring structures of FIGS. 1 and 2, note that the two conductive material deposits of FIG. 2 have replaced the four conductive material deposits of FIG. 1. Thus, the stud-down approach of FIG. 2 is advantageous over the approach of FIG. 1 in that the number of metallic interfaces has been reduced by 50%, and the number of processing steps in the resultant wiring structure has also been reduced.
Another prior art approach which is very similar to the stud-down approach of FIG. 2, is that of the stud-up approach. This approach will be described with reference to FIG. 3. In FIG. 3, elements which are the same as those in FIG. 1 have been given the same reference numerals.
To form the desired wiring structure, vias 107 and 111 are formed in an insulating layer 106 and filled, as was described for FIG. 1. A conductive material (i.e., typically metal) layer is then formed on top of the insulating layer 106 and etched to provide the wiring members 300 and 302. More particularly, the conductive layer is etched such that the wiring member 300 consists of a stud-up 306 and an interconnect 304 formed from the same conductive layer. Similarly the wiring member 302 consists of a stud-up 310 and an interconnect 308 formed from the same conductive layer.
Once the wiring members 300 and 302 have been formed, an insulating layer 312 is formed and typically planarized to be level with the top of the stud-up structures 306 and 310. Another layer of conductive material (i.e., typically metal) is then formed and processed in a similar manner to form the wiring members 314 and 316. The wiring member 314 comprises a stud-up 320 and an interconnect 318 formed of the same conductive layer. Once the wiring structures 314 and 316 have been formed, an insulating layer 324 is formed and typically planarized to be level with the top of the stud-up structure 320. One reference disclosing methods of constructing stud-up structures is the previously cited U.S. Pat. No. 4,541,893.
Like the prior art stud-down approach, the stud-up approach of FIG. 3 is advantageous over the prior art approach of FIG. 1 in that the number of processing steps and metallic interfaces in the wiring structure has been reduced.
Although the stud-down approach of FIG. 2 and stud-up approach of FIG. 3 are both advantageous in the above regards, several contact resistances remain throughout the resultant wiring structures. For example, the interfaces between the conductive materials 230 and 224, 224 and 210, 226 and 212 of FIG. 2 all contribute to an increase in contact resistance. Similarly, the interfaces between the wiring members 314 and 300, 300 and 110, 316 and 302, and 302 and 114 also increase contact resistance.
Although the stud-down and stud-up approaches of FIGS. 2 and 3 represent an improvement, these contact resistances have been found intolerable in the construction and operation of highly dense and compact integrated circuits. Thus, there exists a need for an approach which produces wiring structures having little or no internal contact resistances.
In addition to the contact resistance problem, the prior art has also been deficient in providing a versatile construction method whereby wiring structures having thick lines and thin lines can be constructed. Thick line wiring structures are important where low sheet resistance is required, and thin wiring line structures are important where low capacitance lines are needed. Consequently, a need also exists for a wiring structure approach which also has the versatility of allowing both thick and thin line wiring structures to be constructed.